ZIB, ParTec and Next Silicon AMD, and pro-com are excited to invite you to the upcoming technical Accelerator Hackathon.

Join us in this 1.5 day hackathon to learn about the exciting new HPC approach from NextSilicon. This deep dive covers the programming environment, profiling analysis and optimization approach with dedicated hands-on sessions to allow participants to experience this novel hardware directly.

Workshop AMD partition.

NHR@ZIB operates HPC system Lise consisting of different Compute partitions. Each partition contains a separate compute cluster offering specific hardware. The CPU Genoa partition has been installed in October 2024. The aim of the workshop is to present "AMD EPYC Turin/Genoa CPUs architecture and software stack".

• Date
  • July 15th 2025
  • morning session 09:00-12:00 
  • afternoon session 13:00-16:00
    
• Location
  • online
  • The link to the zoom session will be sent to registered users one day a head of the workshop.
• Lecturer
  • Igor Pasichnyk, Senior Field Application Engineer
  • AMD HPC/AI Center of Excellence
• For questions please send an e-mail to event@nhr.zib.de.

Registration

Due to limited capacity, we would ask you to RSVP until 14th March 2024 by sending an email to event@nhr.zib.de.

Once we receive your registration, the team at ZIB will be in touch regarding the next steps.
Please be aware that in order to participate in the event, you will need to sign an NDA.

Organization

• As this event will be hands-on, please ensure that you bring your own laptop.
• Event location: Zuse Institute Berlin, seminar room
  • How to get to ZIB: see www.zib.de/contact
• HowTo: Activate workshop account and log in to NGT, section Dataflow Engine hardware accelerator on webpage Next-Gen Technology Pool

• material
  • laeuter_amd2025.pdf

Registration

To participate in the online workshop, please register to the email list Training-nhr-bt via the website https://listserv.zib.de/mailman/listinfo/training-nhr-bt. Registration is open until July 11th 2025.